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In this paper we present a Built-In Self Test (BIST) methodology for diagnosis of backend time-dependent dielectric breakdown (BTDDB), via voiding due to electromigration (EM), and stress-induced voiding (SIV) in SRAM cells. Our built-in self test methodology consists of two test procedures. First, faulty cells suffering from wearout mechanisms in the SRAM system are isolated. Then, these faulty cells are tested to determine the cause of wearout.
Processor-level Reliability Simulator for Time- Dependent Gate Dielectric Breakdown
Paper Title (use style: paper title)
Built-in self test methodology for diagnosis of backend wearout mechanisms in SRAM cells
Electric field enhancement caused by porosity in ultra-low-k dielectrics
Georgia Tech Capstone Design Expo
Georgia Tech Capstone Design Expo
G. Tong Zhou – Women in ECE
ECE4871 Fall 2021 Syllabus R1
PPT - ECE4007 Senior Design Project PowerPoint Presentation, free download - ID:5390249
Wearout-aware compiler-directed register assignment for embedded systems
System-level modeling and reliability analysis of microprocessor systems
Porosity-Induced Electric Field Enhancement and Its Impact on Charge Transport in Porous Inter-Metal Dielectrics
Impact of stress acceleration on mixed-signal gate oxide lifetime
Reliable Cache Design with Detection of Gate Oxide Breakdown Using BIST
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